Also, a study of the monitor ROM and the hardware indicates the MZ80A was intended to have a colour output board upgrade similar to the Sharp MZ700 but was never commercially sold. Nibbles Lab spotted this and designed a circuit to upgrade the MZ80A so that it could output video to a colour monitor. Taking this base circuit with some modifications (composite video) I’ve added it into this upgrade. Also as the Character Generator ROM was raised onto the daughter PCB I took the opportunity to use a modern Flash RAM and in so doing allow the storage and switching of multiple Character ROMS, ie. MZ80A, MZ700 I/II, Japanese MZ80K Rom etc. The 32KByte Flash RAM can store 16 character generator ROM sets which can be switched via the attribute RAM (4 ROMS in 1 of 4 blocks) and the control register.
v1.0 Sharp MZ80A 40/80 Colour Board
- The kicad footprint editor, probably my mistake, switched the 2 VLSI gate array footprints around. Correcting this entailed fine soldering and rewiring to correct.
- The oscillator wasnt giving a clean signal so the addition of a 100pF ceramic cap between the U14B pin 4 and ground corrected this. This could be partly due to the above rewiring.
- The gatearray G signal was not connected between the two gatearrays even though it was connected in the circuit diagram, it appeared to be a PCB break.
v1.0 Colour Schematic
In addition to the colour generation circuit, IC15 on the motherboard, the Character Generator ROM, is lifted and replaced by IC U10, a 32KByte Flash RAM. Using bits 7 and 3 from the video attribute output stream of IC U7 and in combination with the latch IC U9, a Character Generator ROM set can be selected. The latch IC U9 selects a set of 4 out of 16 character generator sets within the 32KByte Flash RAM and the attribute bits allow subselection of the 4, thus each character can choose, via the attribute RAM, a possible 4 different character sets at any one time.
v1.0 40/80 Column Schematic
Daughter board with all the relocated IC’s in place.”
Underside of the daughter board. The 34pin CN connector locates to the mainboard Video expansion connector and the remainder are standoffs to extend the original socketed IC's (removed and relocated onto the daughter card) upto the daughter board for rerouting.
Original motherboard with the daughter board in place.
All control is performed through the latch IC U9 at address location 0xDFFF. This address is used by the attribute RAM (it was deemed free when I started the project as it should appear off screen) so a write to this location *may* corrupt the attribute of the last character and only if it is visible whe the Character RAM is scrolled to the bottom. The next release will resolve this bug by using a coded latch so that only a special write sequence will set the latch, other non-coded writes will go to the attribute RAM. This mechanism is needed because the Colour Board does not have access to the IORQ line or the upper address lines so is limited to using the 0xD000:0xD7FF and 0xD800:0xDFFF chip selects.
The table below shows the bit functions of the IC U9 which is a 74HCT373 octal latch. Thus a switch from 40 to 80 column mode requires a write of 0x80 into the control address 0xDFFF.
|0||Character ROM Set Bit 0||Select one of 4 sets of Character Generator ROMS.|
|1||Character ROM Set Bit 1|
|7||40/80 Column Mode||Enable 80 Column mode when set to 1, 40 Column when set to 0 (default)|
The Character Generator ROM on the Colour Board allows for upto 16 CG-ROM images to be stored and selected. On most of the MZ80 machines, the CG-ROM is 2K in size. On the MZ700/800 it is 4K in size. I havent yet obtained all the possible Sharp CG-ROM images so for the time being, the Character Generator Flash RAM IC U10) is loaded as follows:
|Slot||Attribute Bits 7,3||U9 Latch Bits 0:1||Size||ROM||Description|
|0||0,0||0,0||2K||mz-80acg.rom||MZ80A European CG-ROM|
|1||0,1||0,0||2K||MZ80K_cgrom.rom||MZ80K European CG-ROM|
|2||1,0||0,0||2K||MZ80K2E_Jap_cgrom.rom||MZ80K Japanese CG-ROM|
|3||1,1||0,0||2K||MZFONT.rom||Unknown origin CG-ROM|
|4 & 5||0,0 - 0,1||0,1||4K||MZ700_cgrom.rom||MZ700 European CG-ROM (2 banks)|
|6 & 7||1,0 - 1,1||0,1||4K||MZ700_cgrom_jp.rom||MZ700 Japanese CG-ROM (2 banks)|
|8||0,0||1,0||2K||mz-80acg.rom||MZ80A European CG-ROM|
|9||0,1||1,0||2K||MZ80B.rom||MZ80B European CG-ROM|
|10||1,0||1,0||2K||mz-80acg.rom||MZ80A European CG-ROM|
|11||1,1||1,0||2K||mz-80acg.rom||MZ80A European CG-ROM|
|12||0,0||1,1||2K||mz-80acg.rom||MZ80A European CG-ROM|
|13||0,1||1,1||2K||mz-80acg.rom||MZ80A European CG-ROM|
|14||1,0||1,1||2K||mz-80acg.rom||MZ80A European CG-ROM|
|15||1,1||1,1||2K||mz-80acg.rom||MZ80A European CG-ROM|
This image is created by the shell script in the repository, [ABS PATH]/software/tools/make_cgrom.sh and can be executed as follows:
cd [ABS PATH]/software ./tools/make_cgrom.sh
The output image, ie. ../../MZ80A_80COLOUR/software/roms/COLOURBOARD_CG.rom, can be directly flashed into a 28C256 Flash RAM and mounted on the Colour Board.
In order to set a colour on the colour output, an attribute byte is written into the attribute RAM for each character written to the Character RAM. The bits of the attribute RAM have the following function:
|3||Character ROM Bit 0|
|7||Character ROM Bit 1|
To write a Blue character on a Black background for a character 'A' at screen position 0,0 - write 0x41 to Character RAM location 0xD000, write 0x10 to attribute RAM location 0xD800. This assumes Character Generator subset 0.
To select a Character Generator Set, the set is selected by bits 1:0 in IC U9 and the CG ROM, 1 of 4 is selected by the attribute bits 7 & 3 as per the table above.
v2.0 Sharp MZ80A Video Module
As I look to convergence of the Sharp MZ Emulator (which is a series of Sharp MZ machines encapsulated inside an FPGA) and the realisation of the same functionality but in actual hardware on the original machines, the video capabilities need to be upgraded. Keeping to the same theme of not physically modifying the original (vintage) machine but adding additional features which can be removed at will, the next phase is to make a Video Module, which sits in place of the original socketed video IC's and provides all of the functionality found in the Sharp MZ Emulator, ie. the ability to provide a compatible video for all of the Sharp series machines, so should an MZ80B program be run on the Sharp MZ80A with graphics it will appear exactly as an MZ80B.
This design uses a CPLD and an FPGA to provide the required functionality. VHDL from the Sharp MZ Emulator can be adapted to work in the Video Module's FPGA and with sufficient glue logic, drive the video screen of the Sharp MZ80A, an external colour VGA display and at the same time appear to software as the video hardware of any one of the Sharp MZ series machines.
The sections below details the circuit and the PCB which is currently being manufactured.
v2.0 CPLD and FPGA Schematic
The core of this design is an FPGA to replace all the discrete logic on v1.0. The requirements for v2.0 are to add not only the 40/80 column and Colour capabilities of v1.0 but to add compatibility with the MZ80B and its 2 graphics options and the MZ-700 attributes differences. The video memory is instantiated within the FPGA as BRAM along with all the logic.
The CPLD's primary role is to translate 5V from the Sharp logic into 3.3V of the FPGA, the latter not being 5V tolerant. It also takes on replacing some of the logic found in the MB14298/MB14299 gate arrays such as frequency generation and timing.
v2.0 VGA Output Schematic
In contrast to version 1.0, version 2.0 doesnt reuse the existing gate arrays, video shift register, CGROM and RAM, these are removed from the mainboard and simple connectivity is made via their sockets. ie. The video is created by the output (pin 9) of the 74LS165 along with the Sync from the MB14298 (HSY and SYNCH), these locations are lifted off the mainboard and fed from the CPLD.
In addition, true 4 bit RGB output is now fed to the RGB and composite outputs. The Sharp is only monochrome on the MZ80B and 8 colour foreground + 8 colour background on the MZ-700/80A but making this small addition increases flexibility in the range of colours for features such as the MZ80A colour intensity signal and future expansion.
v2.0 Power Supply Schematic
Using FPGA's in a design bring about more complex power requirments. The Sharp MZ80A uses 3 voltages, 12V, 5V and -5V and the FPGA adds 3.3V, 2.5V and 1.2V! Luckily everything on this design is based on 5V taken from an uplifted socket and the CN1 connector from the mainboard, so just adding standard LDO regulators to create the 3 additional voltages along with sufficient decoupling as specified by Altera is all that is required.
- VideoInterface - This is the CPLD and it directly interfaces with the original Sharp MZ80A mainboard hardware being 5V tolerant. It acts as a gateway between the mainboard and the FPGA and provides signals to the mainboard which would have originally been provided by the MB14298/MB14299 gate arrays.
- VideoController - This is the FPGA and it provides all of the video functionality including RAM.
For ease of reading, the following shortnames refer to the corresponding path in this chapter.
|[<ABS PATH>]||The path where this repository was extracted on your system.|
|<CPLD>||VideoInterface_pkg.vhd||The Video Interface configuratioon file.|
|VideoInterface_TopLevel.vhd||The top level design file which joins the pin definitions to the actual Video Interface module.|
|VideoInterface.vhd||The main module describing the required logic for the video interface.|
|<CPLD>/build||VideoInterface.qpf||The Altera project definition file, the entry point in Quartus II for this project.|
|VideoInterface.qsf||The Altera project resource file which desribes the hardware to be used, the settings and the assignment of CPLD pins to be used in the project.|
|VideoInterface_constraints.sdc||The timing contraints file to setup timing definitions and restrictions which guide the compiler during compilation of the project.|
|<FPGA>||VideoController_pkg.vhd||The Video Controller configuratioon file.|
|VideoController_TopLevel.vhd||The top level design file which joins the pin definitions to the actual Video Controller module.|
|VideoController.vhd||The main module describing the required logic for the video controller.|
|<CPLD>/build||VideoController.qpf||The Altera project definition file, the entry point in Quartus II for this project.|
|VideoController.qsf||The Altera project resource file which desribes the hardware to be used, the settings and the assignment of FPGA pins to be used in the project.|
|VideoController_constraints.sdc||The timing contraints file to setup timing definitions and restrictions which guide the compiler during compilation of the project.|
|Clock_*||Refactored Altera PLL definitions for various development board source clocks. These need to be made more generic for eventual inclusion of Xilinx fabric.|
|<FPGA>/devices||RAM||Dual Port RAM|
Quartus Prime in Docker
Clone the repository:
cd ~ git clone https://github.com/pdsmart/zpu.git cd zpu/docker/QuartusPrime
Current configuration will build a Lite version of Quartus Prime. If you want to install the Standard version, before building the docker image:
Edit: zpu/docker/QuartusPrime/Dockerfile.13.0.1 Uncomment: '#ARG QUARTUS=QuartusSetup-184.108.40.206.run' Comment out: 'ARG QUARTUS=QuartusSetupWeb-220.127.116.11.run'
If you have a license file:
Copy: <your license file> to zpu/docker/QuartusPrime/files/license.dat Edit: zpu/docker/QuartusPrime/run.sh Change: MAC_ADDR="02:50:dd:72:03:01" so that is has the MAC Address of your license file.
Build the docker image:
docker build -f Dockerfile.13.0.1 -t quartus-ii-13.0.1 --build-arg user_uid=`id -u` --build-arg user_gid=`id -g` --build-arg user_name=`whoami` .
For Quartus Prime 13.1 replace 13.0.1 with the necessary version. Quartus Prime 13.0.1 supports the older MAX CPLD devices. Quartus Prime 13.1 supports the older Cyclone III devices.
Setup your X DISPLAY variable to point to your xserver:
export DISPLAY=<x server ip or hostname>:<screen number or :<screen number>> # ie. export DISPLAY=192.168.1.1:0
On your X server machine, issue the command:
xhost + # or xhost <ip of docker host> to maintain security on a non private network.
Setup your project directory accessible to Quartus.
Edit: zpu/docker/QuartusPrime/run.sh Change: PROJECT_DIR_HOST=<location on your host you want to access from Quartus Prime> Change: PROJECT_DIR_IMAGE=<location in Quartus Prime running container to where the above host directory is mapped> # ie. PROJECT_DIR_HOST=/srv/quartus PROJECT_DIR_IMAGE=/srv/quartus
Run the image using the provided bash script ‘run_quartus.sh’. This script
This will start Quartus Prime and also an interactive bash shell.
On first start it currently asks for your license file, click 'Run the Quartus Prime software' and then OK. It will ask you this question everytime you start a new container albeit Im looking for a work around.
The host devices are mapped into the running docker container so that if you connect a USB Blaster it will be seen within the Programmer tool. As part of the installation I install the udev rules for USB-Blaster and USB-Blaster II as well as the Arrow USB-Blaster driver for use with the CYC1000 dev board.
To stop quartus prime:
# Either exit the main Quartus Prime GUI window via File->Exit # or docker stop quartus
The Gnu Public License v3
The source files are distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program. If not, see http://www.gnu.org/licenses/.