The Sharp MZ80A was a personal computer from the 1980's and Sharp considered that a 40 column screen with 25 rows was sufficient for the home market. For most purposes it was sufficient but with the rise of CP/M requiring 80 column displays there was a number of external vendors who provided add on boards to enhance the video capabilities. Most of these boards used bespoke hardware solutions such as the addition of a 6845 CRT controller and non-standard Monitor ROMS. A study of the MZ80A hardware though revealed it was identical to the more costly business machine, the MZ80B. The hardware in the MZ80A had been wired differently to cripple its capabilities, presumably for marketing reasons, so by rerouting the wiring it is fairly easy to achieve an 80 column display. The v1.0 upgrade makes such a change, it removes the video controller gate arrays off the main board and reroutes the wiring on a daughter PCB to achieve 40/80 column switched display.

Also, a study of the monitor ROM and the hardware indicates the MZ80A was intended to have a colour output board upgrade similar to the Sharp MZ700 but was never commercially sold. Nibbles Lab spotted this and designed a circuit to upgrade the MZ80A so that it could output video to a colour monitor. Taking this base circuit with some modifications (composite video) I’ve added it into this upgrade. Also as the Character Generator ROM was raised onto the daughter PCB I took the opportunity to use a modern Flash RAM and in so doing allow the storage and switching of multiple Character ROMS, ie. MZ80A, MZ700 I/II, Japanese MZ80K Rom etc. The 32KByte Flash RAM can store 16 character generator ROM sets which can be switched via the attribute RAM (4 ROMS in 1 of 4 blocks) and the control register.

Forwarding the design, v2.0 expands on v1.0 functionality using an FPGA and provides additional functionality such as pixel mapped graphics found on the MZ80B and the intention to include the colour pixel mapped graphics from the MZ-800.

v1.0 Sharp MZ80A 40/80 Colour Board

The gallery pictures and the hardware section below display v1.0 of the board. A few issues existed during production of this board:-
  1. The kicad footprint editor, probably my mistake, switched the 2 VLSI gate array footprints around. Correcting this entailed fine soldering and rewiring to correct.
  2. The oscillator wasnt giving a clean signal so the addition of a 100pF ceramic cap between the U14B pin 4 and ground corrected this. This could be partly due to the above rewiring.
  3. The gatearray G signal was not connected between the two gatearrays even though it was connected in the circuit diagram, it appeared to be a PCB break.
I have corrected the circuit diagram and was originally intending to produce a v1.1 PCB but new ideas came up and I jumped to v2.0 using CPLD and FPGA technology to increase functionality and decrease size. v2.0 renames the project to the Sharp MZ80A Video Module as it not only provides 40/80 column display and colour but also MZ80B graphics and capacity to add a lot more features.

v1.0 Hardware

v1.0 Colour Schematic

Sheet 2

This portion is the colour generation circuit. Basically it adds a 2K Static RAM into the memory mapped location 0xD800 - 0xDFFF which is called the attribute RAM. The attribute RAM can be accessed by the CPU for read/write and the video circuitry will periodically scan each location, both Character RAM and the new attribute RAM. As each byte is scanned by the video circuitry, its output is captured by IC U7 and used to generate a foreground and background colour signal according to the bits 6:4 (foreground) and 2:0 (background). Each bit pair 6+2, 5+1, 4+0 form the 3 basic colours, RGB and each blended with the monochrome video signal to create the necessary RGB Video signal. The RGB is only digital, ie on/off, so a maximum of 8 colours foreground and 8 colours background can be generated. The actual colour seen on a monitor is controlled by the resistors R11:R19, R13:R1, R15:R17 and R20/R22. As RGB on modern monitors is analogue, the voltage presented to the monitor via these resistor networks controls the colour. For Composite monitors, Q1 blends RGB and and composite Sync.

In addition to the colour generation circuit, IC15 on the motherboard, the Character Generator ROM, is lifted and replaced by IC U10, a 32KByte Flash RAM. Using bits 7 and 3 from the video attribute output stream of IC U7 and in combination with the latch IC U9, a Character Generator ROM set can be selected. The latch IC U9 selects a set of 4 out of 16 character generator sets within the 32KByte Flash RAM and the attribute bits allow subselection of the 4, thus each character can choose, via the attribute RAM, a possible 4 different character sets at any one time.

v1.0 40/80 Column Schematic

Sheet 3

This portion is the 40/80 column character generation circuit. It is basically the same circuit as seen in the Sharp MZ80B. The Sharp MZ80A has the same chipset but it is wired differently, ie capped! Using this circuit, the chips are rewired and thus able to selectably switch between 40 and 80 character modes. Latch IC U9 provides the switching signal.

v1.0 PCB

PCB TopSide

Daughter board with all the relocated IC’s in place.”

PCB UnderSide

Underside of the daughter board. The 34pin CN connector locates to the mainboard Video expansion connector and the remainder are standoffs to extend the original socketed IC's (removed and relocated onto the daughter card) upto the daughter board for rerouting.

PCB UnderSide

Original motherboard with the daughter board in place.

v1.0 Software

v1.0 is hardware only controlled by software which resides in the Rom Filing System or the SA-1510 monitor. The only 'soft' ware is the Character Generator ROM and also to know how to program the hardware.

All control is performed through the latch IC U9 at address location 0xDFFF. This address is used by the attribute RAM (it was deemed free when I started the project as it should appear off screen) so a write to this location *may* corrupt the attribute of the last character and only if it is visible whe the Character RAM is scrolled to the bottom. The next release will resolve this bug by using a coded latch so that only a special write sequence will set the latch, other non-coded writes will go to the attribute RAM. This mechanism is needed because the Colour Board does not have access to the IORQ line or the upper address lines so is limited to using the 0xD000:0xD7FF and 0xD800:0xDFFF chip selects.

The table below shows the bit functions of the IC U9 which is a 74HCT373 octal latch. Thus a switch from 40 to 80 column mode requires a write of 0x80 into the control address 0xDFFF.

Bit Function Description
0 Character ROM Set Bit 0 Select one of 4 sets of Character Generator ROMS.
1 Character ROM Set Bit 1  
2 Unused  
3 Unused  
4 Unused  
5 Unused  
6 Unused  
7 40/80 Column Mode Enable 80 Column mode when set to 1, 40 Column when set to 0 (default)

The Character Generator ROM on the Colour Board allows for upto 16 CG-ROM images to be stored and selected. On most of the MZ80 machines, the CG-ROM is 2K in size. On the MZ700/800 it is 4K in size. I havent yet obtained all the possible Sharp CG-ROM images so for the time being, the Character Generator Flash RAM IC U10) is loaded as follows:

Slot Attribute Bits 7,3 U9 Latch Bits 0:1 Size ROM Description
0 0,0 0,0 2K mz-80acg.rom MZ80A European CG-ROM
1 0,1 0,0 2K MZ80K_cgrom.rom MZ80K European CG-ROM
2 1,0 0,0 2K MZ80K2E_Jap_cgrom.rom MZ80K Japanese CG-ROM
3 1,1 0,0 2K MZFONT.rom Unknown origin CG-ROM
4 & 5 0,0 - 0,1 0,1 4K MZ700_cgrom.rom MZ700 European CG-ROM (2 banks)
6 & 7 1,0 - 1,1 0,1 4K MZ700_cgrom_jp.rom MZ700 Japanese CG-ROM (2 banks)
8 0,0 1,0 2K mz-80acg.rom MZ80A European CG-ROM
9 0,1 1,0 2K MZ80B.rom MZ80B European CG-ROM
10 1,0 1,0 2K mz-80acg.rom MZ80A European CG-ROM
11 1,1 1,0 2K mz-80acg.rom MZ80A European CG-ROM
12 0,0 1,1 2K mz-80acg.rom MZ80A European CG-ROM
13 0,1 1,1 2K mz-80acg.rom MZ80A European CG-ROM
14 1,0 1,1 2K mz-80acg.rom MZ80A European CG-ROM
15 1,1 1,1 2K mz-80acg.rom MZ80A European CG-ROM

This image is created by the shell script in the repository, [ABS PATH]/software/tools/make_cgrom.sh and can be executed as follows:

cd [ABS PATH]/software

The output image, ie. ../../MZ80A_80COLOUR/software/roms/COLOURBOARD_CG.rom, can be directly flashed into a 28C256 Flash RAM and mounted on the Colour Board.

In order to set a colour on the colour output, an attribute byte is written into the attribute RAM for each character written to the Character RAM. The bits of the attribute RAM have the following function:

Bit Function
0 Background Blue
1 Background Red
2 Background Green
3 Character ROM Bit 0
4 Foreground Blue
5 Foreground Red
6 Foreground Green
7 Character ROM Bit 1

To write a Blue character on a Black background for a character 'A' at screen position 0,0 - write 0x41 to Character RAM location 0xD000, write 0x10 to attribute RAM location 0xD800. This assumes Character Generator subset 0.

To select a Character Generator Set, the set is selected by bits 1:0 in IC U9 and the CG ROM, 1 of 4 is selected by the attribute bits 7 & 3 as per the table above.

v2.0 Sharp MZ80A Video Module

Version 1.0 has been working well for almost a year now with a lot of run time whilst using it to develop my MZ80A software and hardware upgrades. It is consistently driving the original inbuilt monitor and an external colour LCD. It is a proven design and apart from the faults in the PCB layout (footprints of the MB14298 and MB14299 where swapped) it is an ideal choice if your looking to upgrade an MZ80A to run CP/M or similar software.

As I look to convergence of the Sharp MZ Emulator (which is a series of Sharp MZ machines encapsulated inside an FPGA) and the realisation of the same functionality but in actual hardware on the original machines, the video capabilities need to be upgraded. Keeping to the same theme of not physically modifying the original (vintage) machine but adding additional features which can be removed at will, the next phase is to make a Video Module, which sits in place of the original socketed video IC's and provides all of the functionality found in the Sharp MZ Emulator, ie. the ability to provide a compatible video for all of the Sharp series machines, so should an MZ80B program be run on the Sharp MZ80A with graphics it will appear exactly as an MZ80B.

This design uses a CPLD and an FPGA to provide the required functionality. VHDL from the Sharp MZ Emulator can be adapted to work in the Video Module's FPGA and with sufficient glue logic, drive the video screen of the Sharp MZ80A, an external colour VGA display and at the same time appear to software as the video hardware of any one of the Sharp MZ series machines.

The sections below details the circuit and the PCB which is currently being manufactured.

v2.0 Hardware

v2.0 CPLD and FPGA Schematic

Sheet 3

The core of this design is an FPGA to replace all the discrete logic on v1.0. The requirements for v2.0 are to add not only the 40/80 column and Colour capabilities of v1.0 but to add compatibility with the MZ80B and its 2 graphics options and the MZ-700 attributes differences. The video memory is instantiated within the FPGA as BRAM along with all the logic.

The CPLD's primary role is to translate 5V from the Sharp logic into 3.3V of the FPGA, the latter not being 5V tolerant. It also takes on replacing some of the logic found in the MB14298/MB14299 gate arrays such as frequency generation and timing.

v2.0 VGA Output Schematic

Sheet 4

In contrast to version 1.0, version 2.0 doesnt reuse the existing gate arrays, video shift register, CGROM and RAM, these are removed from the mainboard and simple connectivity is made via their sockets. ie. The video is created by the output (pin 9) of the 74LS165 along with the Sync from the MB14298 (HSY and SYNCH), these locations are lifted off the mainboard and fed from the CPLD.

In addition, true 4 bit RGB output is now fed to the RGB and composite outputs. The Sharp is only monochrome on the MZ80B and 8 colour foreground + 8 colour background on the MZ-700/80A but making this small addition increases flexibility in the range of colours for features such as the MZ80A colour intensity signal and future expansion.

v2.0 Power Supply Schematic

Sheet 2

Using FPGA's in a design bring about more complex power requirments. The Sharp MZ80A uses 3 voltages, 12V, 5V and -5V and the FPGA adds 3.3V, 2.5V and 1.2V! Luckily everything on this design is based on 5V taken from an uplifted socket and the CN1 connector from the mainboard, so just adding standard LDO regulators to create the 3 additional voltages along with sufficient decoupling as specified by Altera is all that is required.

v2.0 PCB

PCB TopSide

PCB UnderSide

v2.0 Software

The software is basically hardware described in a HDL, in this case VHDL. All the designs use VHDL 2008 and run on Altera fabric. There are two distinct components of the Video Module:
  • VideoInterface - This is the CPLD and it directly interfaces with the original Sharp MZ80A mainboard hardware being 5V tolerant. It acts as a gateway between the mainboard and the FPGA and provides signals to the mainboard which would have originally been provided by the MB14298/MB14299 gate arrays.
  • VideoController - This is the FPGA and it provides all of the video functionality including RAM.

Repository Structure


For ease of reading, the following shortnames refer to the corresponding path in this chapter.

Short Name  
[<ABS PATH>] The path where this repository was extracted on your system.


Folder RTL File Description
<CPLD> VideoInterface_pkg.vhd The Video Interface configuratioon file.
  VideoInterface_TopLevel.vhd The top level design file which joins the pin definitions to the actual Video Interface module.
  VideoInterface.vhd The main module describing the required logic for the video interface.
<CPLD>/build VideoInterface.qpf The Altera project definition file, the entry point in Quartus II for this project.
  VideoInterface.qsf The Altera project resource file which desribes the hardware to be used, the settings and the assignment of CPLD pins to be used in the project.
  VideoInterface_constraints.sdc The timing contraints file to setup timing definitions and restrictions which guide the compiler during compilation of the project.
<FPGA> VideoController_pkg.vhd The Video Controller configuratioon file.
  VideoController_TopLevel.vhd The top level design file which joins the pin definitions to the actual Video Controller module.
  VideoController.vhd The main module describing the required logic for the video controller.
<CPLD>/build VideoController.qpf The Altera project definition file, the entry point in Quartus II for this project.
  VideoController.qsf The Altera project resource file which desribes the hardware to be used, the settings and the assignment of FPGA pins to be used in the project.
  VideoController_constraints.sdc The timing contraints file to setup timing definitions and restrictions which guide the compiler during compilation of the project.
  Clock_* Refactored Altera PLL definitions for various development board source clocks. These need to be made more generic for eventual inclusion of Xilinx fabric.
<FPGA>/devices RAM Dual Port RAM

Quartus Prime in Docker

Installing Quartus Prime can be tedious and time consuming, especially as the poorly documented linux installation can lead to a wrong mix or missing packages which results in a non-functioning installation. To ease the burden I have pieced together a Docker Image containing Ubuntu, the necessary packages and Quartus Prime 13.0sp1 and 13.1. Quartus Prime 13.0sp1 is needed for the CPLD compilation and Quartus Prime 13.1 for the FPGA.
  1. Clone the repository:

     cd ~
     git clone https://github.com/pdsmart/zpu.git
     cd zpu/docker/QuartusPrime

    Current configuration will build a Lite version of Quartus Prime. If you want to install the Standard version, before building the docker image:
     Edit:        zpu/docker/QuartusPrime/Dockerfile.13.0.1
     Uncomment:   '#ARG QUARTUS=QuartusSetup-'
     Comment out: 'ARG QUARTUS=QuartusSetupWeb-'

    If you have a license file:

     Copy: <your license file> to zpu/docker/QuartusPrime/files/license.dat
     Edit:  zpu/docker/QuartusPrime/run.sh
     Change: MAC_ADDR="02:50:dd:72:03:01" so that is has the MAC Address of your license file.

    Build the docker image:

     docker build -f Dockerfile.13.0.1 -t quartus-ii-13.0.1 --build-arg user_uid=`id -u`  --build-arg user_gid=`id -g` --build-arg user_name=`whoami` .

    For Quartus Prime 13.1 replace 13.0.1 with the necessary version. Quartus Prime 13.0.1 supports the older MAX CPLD devices. Quartus Prime 13.1 supports the older Cyclone III devices.
  2. Setup your X DISPLAY variable to point to your xserver:

     export DISPLAY=<x server ip or hostname>:<screen number or :<screen number>>
     # ie. export DISPLAY=

    On your X server machine, issue the command:

     xhost +
     # or xhost <ip of docker host> to maintain security on a non private network.
  3. Setup your project directory accessible to Quartus.

     Edit:        zpu/docker/QuartusPrime/run.sh
     Change:      PROJECT_DIR_HOST=<location on your host you want to access from Quartus Prime>
     Change:      PROJECT_DIR_IMAGE=<location in Quartus Prime running container to where the above host directory is mapped>
     # ie. PROJECT_DIR_HOST=/srv/quartus
  4. Run the image using the provided bash script ‘run_quartus.sh’. This script


    This will start Quartus Prime and also an interactive bash shell.
    On first start it currently asks for your license file, click 'Run the Quartus Prime software' and then OK. It will ask you this question everytime you start a new container albeit Im looking for a work around.

    The host devices are mapped into the running docker container so that if you connect a USB Blaster it will be seen within the Programmer tool. As part of the installation I install the udev rules for USB-Blaster and USB-Blaster II as well as the Arrow USB-Blaster driver for use with the CYC1000 dev board.
  5. To stop quartus prime:

     # Either exit the main Quartus Prime GUI window via File->Exit
     # or
     docker stop quartus


The original Colour circuit used in v1.0 is copyright Nibbles Lab 2018 and was adapted for this design. Where I have used or based any component on a 3rd parties design I have included the original authors copyright notice within the headers or given due credit. All 3rd party software, to my knowledge and research, is open source and freely useable, if there is found to be any component with licensing restrictions, it will be removed from this repository and a suitable link/config provided.


Not withstanding the Colour Module and any future limiting restrictions, this design, hardware and software, is licensed under the GNU Public Licence v3.

The Gnu Public License v3

The source and binary files in this project marked as GPL v3 are free software: you can redistribute it and-or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.

The source files are distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program. If not, see http://www.gnu.org/licenses/.