This is a collection of projects that I am currently working on in my spare time and also a collection of past projects as I am able to rescue them. All of these projects are made open source so feel free to collaborate, fork or add issues.

Browse using this markdown website or view directly in the Repository and use if suitable for your needs or projects.

Project Status

Project Date Status
MZ80A RFS 24/03/20 More major changes, added an SD card to the design, updated the RFS to access Sharp MZ80A programs on the SD card and also updated CPM so that it can access the SD card as a set of virtual 16MB fixed drives.
  25/02/20 Major changes as I have implemented CPM and wrote the CBIOS / Ansi Terminal Emulator in the banked Rom. Currently beta level, CPM boots and runs fine, just the keyboard mappings need enhancing and some tweaks to the Ansi Terminal Emulator. Currently adding an SD Card into the hardware design and will add the software shortly thereafter.
  23/8/19 Version 1.0 of the hardware and software are reliably running but Im in process of making a v1.1 PCB with corrections and additional logic to enable writing by the MZ80A to the Flash RAM.
tranZPUter 24/03/20 Debugged the hardware and made changes resulting in v1.1a of the hardware design. Slowly working out the FSM in VHDL to read/write between the FPGA and the Z80 Host. Also still waiting on me going Eureka and finding the bug in the L2 to L1 cache when using SDRAM!!!
  15/12/19 Updated with the new ZPU Evo core and working SDRAM controller, 48K BRAM and 4MByte SDRAM so external applications can run (needed as main transZPUter app will run in SDRAM and more BRAM will be allocated to cache).
  23/9/19 Waiting on the ZPU Evo. Hardware designed, tested and test ditties written to check that the FPGA can Master the Z80 Bus and utilize it’s hardware. Started the software (in C) framework based on the SharpMZ Emulator code.
ZPU Evo 28/01/20 The SDRAM, both vanilla and cached versions (1 row per bank cache) are working and pass all the memory tests at 100MHz. Unfortunately when using the SDRAM for program execution it highlighted a bug in the ZPU Evo which I have been trying to resolve. The bug is timing related and is between L2 to L1 and only shows up due to the timing delay of SDRAM. Using the cached SDRAM the bug is not so frequent but it needs resolving as the transzputer project needs SDRAM for applicaiton execution. To be resolved shortly!
  23/12/19 Replaced megacore dual-port BRAM used for L2 cache with inferred RAM to aid in portability and updated write-thru to work at byte level (for self modifying code). Found and corrected a byte/half-word write bug which always defaulted to read-update-write. Changed the multiplication logic to meet timing (use of variable/combinational logic was causing significant negative slack impact). Fixed the timing for L2 Cache access. SDRAM now working for Wishbone and system bus reliably at 75MHz and meeting timing constraints. Still having issues running reliably > 75MHz no matter how the timing is arranged, still a work in progress. Used Signal Tap but cannot see reason. Still to add Burst mode for L2 Cache from SDRAM, design worked out using BRAM just have to code it.
  31/10/19 The ZPU Evo is complete, I would say at Beta status until it is fully running in the SharpMZ project when I will stress it and add extra instructions. Debugging the WishBone SDRAM Controller, adding burst mode for L2 Cache Fill. Once the SDRAM Controller is fully working progress can be made on it’s dependents, for example the tranZPUter uses the Cyclone 10LP which has limited BRAM memory but an external 8M SDRAM chip so the SDRAM Controller is currently a showstopper.
SharpMZ 7/6/19 Many fixes and updates have been made compared to the MiSTer_Devel released version 1.0 and started to add an IOCTL module so that the ZPU Evo can be embedded and take control of the emulator hardware. IOCTL is how MiSTer_Devel allows the HPS to control the target emulator so I’m keeping this mechanism in place for consistency.
dPWR 12/11/19 dPWR has been running reliably for 4 years, it needs tidying up a bit in terms of instructions, user guide and howto program additional modules/devices.
jDPWR 16/11/19 I started to write this Java version based on dPWR two years back but it got sidelined when I started the VHDL projects. I will finish it but no definite date yet.
MZ80A 80Col 23/8/19 Version 1.0 is reliable but I want to correct the control register access such that a write to the last bytes of attribute RAM doesnt occur when changing PCG bank or switching between 40/80 col.

Project Dependencies

Project Dependents Notes
ZPU Evo tranZPUter The tranZPUter uses the ZPU Evo as it’s primary soft processor
ZPU Evo SharpMZ The SharpMZ Emulator will have the ZPU Evo embedded to act as the IO and User Interface processor making the project less dependent on FPGA resources such as the embedded HPS on the Cyclone V.

Bug Tracking

Project Ticket # Date Status
CP/M A000001 26/02/20 Ansi emulation not recognising clear screen.
  A000002 26/02/20 CR being mapped to LF in the Screen I/O.
  A000003 28/02/20 Physical disks not correctly assigned when switch disk parameter blocks so that ROM drive is A. Need to Map CPM Logical to FDC Physical.
MZ80A RFS B000001 23/08/19 A write to flash clashes with the page register.
ZPU Evo C000001 28/01/20 L2 to L1 timing results in one 32bit word being incorrectly placed in the L1 cache. The bug occurs on program jumps and the word is from the previous next of PC location. Only occurs when using SDRAM.
tranZPUter D000001 28/02/20 CYC_D0 not 3.3V compliant, operating at 2.5V GPIO0 is specified as a General Purpose IO yet a dig into the schematic shows it is tied to an RC circuit, removal of C15 is necessary to use this pin for bidir IO
SharpMZ E    
dPWR F    
jDPWR G    
MZ80A 80Col H000001 23/08/19 A write to the control register bleeds into the attribute ram as they share the same location. Needs a coded latch to seperate the write signals.