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Teil 1 — Einfuehrung
Dieses Handbuch richtet sich an Entwickler, die den Sharp MZ Serie FPGA-Emulator auf der MiSTer-Plattform verstehen, modifizieren oder erweitern moechten. Es behandelt die vollstaendige Architektur — vom VHDL/SystemVerilog-Design, das im Cyclone V FPGA synthetisiert wird, ueber das HPS-FPGA-Brueckenprotokoll bis zum C++-Unterstuetzungscode, der auf dem ARM Cortex-A9 Hard Processor System (HPS) laeuft.
| Background |
What you will gain |
| FPGA / HDL developer |
Deep understanding of the VHDL architecture, clock domains, memory map, and how to add hardware modules |
| C / C++ developer |
How the MiSTer main binary communicates with the FPGA over SPI |
| MiSTer core developer |
Integration points with the MiSTer framework (hps_io, sys_top, IOCTL protocol) |
| Student / hobbyist |
End-to-end view of a non-trivial FPGA emulation project |
Emulierte Maschinen
| Model |
Series |
Status |
Key differences |
| MZ-80K |
Personal |
Complete |
Original 1978 model, 2MHz Z80, monochrome 40x25 |
| MZ-80C |
Personal |
Complete |
Cost-reduced MZ-80K |
| MZ-1200 |
Personal |
Complete |
Compact desktop MZ-80A predecessor |
| MZ-80A |
Personal |
Complete |
Enhanced MZ-80K, most popular model |
| MZ-700 |
Personal |
Complete |
Colour display, different keyboard matrix |
| MZ-800 |
Personal |
Partial |
Extended MZ-700, graphics modes |
| MZ-80B |
Business |
Complete |
Business series, 80-column display, GRAM, Z80 PIO |
| MZ-2000 |
Business |
Partial |
Enhanced MZ-80B, FDD support, APSS tape |
Das MiSTer-Projekt verwendet das Terasic DE10-Nano Board, basierend auf dem Intel (Altera) Cyclone V SoC.
| Parameter |
Value |
| FPGA device |
Cyclone V SE 5CSEBA6U23I7 |
| Logic elements |
41,910 |
| Embedded memory |
5,662 Kbits |
| HPS |
Dual-core ARM Cortex-A9 @ 800MHz |
| DDR3 |
1GB (HPS side) |