Sharp MZ-80A Video Module — User Manual
Video Module User Manual
The Sharp MZ-80A Video Module is a hardware upgrade that restores and extends the video capabilities of the Sharp MZ-80A. The MZ-80A shares identical hardware with the MZ-80B but was shipped with 80-column mode and colour output permanently disabled in the factory wiring. The Video Module corrects this, adds a switchable 32 KB Flash RAM Character Generator ROM holding up to 16 character sets, and — in its v2.0 FPGA incarnation — adds full VGA output, 640×200 pixel graphics, GPU acceleration, and emulation of every Sharp MZ video mode from the MZ-80K through to the MZ-2000.
This manual covers hardware selection, physical installation, day-to-day use, and the complete register reference for both v1.1 and v2.0. Source files, schematic PDFs, and Quartus project files are available from the project repository.
Which Version Should I Choose?
Two hardware generations of the Video Module exist. The right choice depends on what you already have installed in your MZ-80A and what level of video capability you need.
| Feature | v1.1 (discrete) | v2.0 (FPGA) |
|---|---|---|
| 40 / 80 column switching | Yes | Yes |
| 8-colour RGB output | Yes | Yes |
| Composite video output | Yes | No |
| VGA output (640×480 / 800×600 / 1024×768) | No | Yes |
| 16-slot Character Generator ROM | Yes | Yes |
| 640×200 / 320×200 pixel graphics | No | Yes |
| GPU acceleration | No | Yes |
| Sharp MZ video mode emulation | No | Yes (MZ-80K/80C/1200/80A/700/800/80B/2000) |
| Programmable colour palette | No | Yes |
| tranZPUter board required | No | Yes |
| Discrete 74-series ICs | Yes | No |
Choose v1.1 if you want a standalone discrete-component upgrade on an otherwise standard MZ-80A. It provides 40/80 column switching and 8-colour RGB output with no dependency on any other upgrade board.
Choose v2.0 if the tranZPUter board is already installed in your MZ-80A and you want VGA output, pixel graphics, and full video mode emulation. The v2.0 board connects via the tranZPUter expansion connector and cannot be installed without the tranZPUter.
Note on v1.0: v1.0 was a prototype run with five known hardware defects. It is not recommended. If you have a v1.0 board, see the troubleshooting section for known errata and contact the project page for a v1.1 replacement.
What You Need
v1.1 — Discrete Component Version- Video Module v1.1 PCB — available assembled or as a self-build kit. The assembled version has the 74-series ICs and raiser pin arrays pre-fitted.
- Sharp MZ-80A — any revision. The MZ-80B is electrically identical and is also compatible.
- 28C256 (32 KB) Flash RAM pre-programmed with
COLOURBOARD_CG.rom— this is the Character Generator ROM image containing the 16 pre-built character sets. Available pre-programmed from the project page or you can program a blank 28C256 yourself with a TL866 II+ or compatible programmer. - Colour monitor with RGB (SCART or separate R/G/B) or composite video input. A period-appropriate monitor such as a Philips CM8833 works well; any modern monitor with a SCART adapter will also work.
- DIP sockets for IC8, IC9, and IC15 on the MZ-80A motherboard (supplied with the kit).
- Chip puller / IC extractor, fine soldering iron, and solder.
- Anti-static precautions — ESD wrist strap and mat.
- 34-pin ribbon cable (supplied with the board) for the motherboard Video expansion connector.
- Video Module v2.0 PCB — FPGA board, available assembled or as a kit.
- Sharp MZ-80A with tranZPUter board already installed. The Video Module v2.0 connects to the tranZPUter expansion connector; it cannot be used without the tranZPUter.
- VGA monitor — any standard VGA monitor. The FPGA can output 640×480@60 Hz, 800×600@60 Hz, or 1024×768@60 Hz.
- Altera USB-Blaster (or compatible clone) JTAG programmer — required to program the CPLD and FPGA on first install and after any firmware update.
- Quartus Prime 13.0.1 — required to program the CPLD (
VideoInterface.jic). Free download from Intel/Altera. - Quartus Prime 13.1 — required to program the FPGA (
VideoController.jic). Free download from Intel/Altera. - Anti-static precautions — ESD wrist strap and mat.
Installing the Video Module v1.1
The v1.1 board is a daughter board that sits above ICs 8, 9, and 15 on the MZ-80A motherboard. Those ICs are removed and replaced with DIP sockets; the daughter board's raiser pin arrays seat into the sockets, re-exporting the signals with the Video Module logic interposed. A 34-pin ribbon cable connects the board to the motherboard's Video expansion connector. The following steps summarise the installation — refer to the full 35-step illustrated guide in the project documentation for photographs and exact component locations.
Installation Steps
- Power off and unplug the MZ-80A. Remove the outer case lid and set it aside.
- Ground yourself using an ESD wrist strap clipped to the chassis.
- Locate IC8, IC9, and IC15 on the MZ-80A motherboard. IC15 is the 2 KB Character Generator ROM. IC8 and IC9 are the video gate array ICs. Consult the motherboard overlay diagram in the MZ-80A service manual if uncertain.
- Carefully remove IC8, IC9, and IC15 using a chip puller. Work from corner to corner to avoid bending pins. Set the removed ICs aside in an anti-static bag — they are not re-installed; the daughter board subsumes their function.
- Install DIP sockets in the vacated IC8, IC9, and IC15 footprints. Solder each pin carefully. Inspect for solder bridges before proceeding.
- Seat the Video Module daughter board onto the three DIP sockets using the raiser pin arrays on the underside of the board. The board should sit level; press firmly until the raiser pins are fully engaged in the sockets.
- Connect the 34-pin ribbon cable between the J1 connector on the daughter board and the Video expansion connector on the MZ-80A motherboard. Ensure pin 1 alignment (the red stripe on the ribbon aligns with the pin 1 marker on both connectors).
- Install the pre-programmed 28C256 Flash RAM (CG-ROM) in socket U10 on the daughter board. Align the notch with the socket and press firmly. This device replaces the original 2 KB Character Generator ROM and holds the full 16-slot character set image.
- Route the RGB / composite output connector to a convenient point at the rear of the case. A blanking plate with the connector cutout is available from the project page, or use an existing unused aperture in the case rear panel.
- Reassemble the MZ-80A case and connect the colour monitor to the output connector.
- Power on and test — the MZ-80A should boot normally. The display should appear on the colour monitor in 40-column mode with white characters on a black background (the default attribute state). Proceed to Using the Module — v1.x to switch to 80-column mode and set character colours.
If you need to program a blank 28C256 yourself, use a TL866 II+ or compatible programmer with the
minipro utility. The image file is COLOURBOARD_CG.rom, available in the releases/ directory of the project repository:
minipro --infoic /path/to/minipro/infoic.xml -p AT28C256 -s -w COLOURBOARD_CG.rom
Verify after programming:
minipro --infoic /path/to/minipro/infoic.xml -p AT28C256 -s -y COLOURBOARD_CG.rom
Installing the Video Module v2.0
The v2.0 board is an FPGA-based design that connects to the tranZPUter expansion connector inside the MZ-80A. The tranZPUter board must already be installed and verified working before fitting the v2.0 Video Module. The FPGA and CPLD on the board must be programmed via JTAG before first use. The following steps summarise the installation — refer to the full 35-step illustrated guide in the project documentation for photographs and exact connector locations.
Installation Steps
- Verify the tranZPUter board is installed and the MZ-80A boots correctly with it fitted. The Video Module v2.0 depends on the tranZPUter's bus interface and power rails.
- Power off and unplug the MZ-80A. Ground yourself with an ESD wrist strap.
- Connect the Video Module v2.0 board to the tranZPUter expansion connector. The board's edge connector aligns with the tranZPUter expansion header — ensure pin 1 alignment before applying pressure.
- Connect the USB-Blaster JTAG programmer to the JTAG header on the Video Module board. Do not power on the MZ-80A yet.
- Power on the MZ-80A so that the board's JTAG targets are powered.
- Programme the CPLD using Quartus Prime 13.0.1. Open the Quartus Programmer, select the
VideoInterface.jicfile, select the CPLD device in the JTAG chain, and click Start. Wait for the programming to complete successfully. - Programme the FPGA using Quartus Prime 13.1. Open the Quartus Programmer, select the
VideoController.jicfile, select the FPGA device in the JTAG chain, and click Start. Wait for the programming to complete successfully. - Disconnect the JTAG programmer and connect a VGA monitor to the VGA output connector on the Video Module board.
- Power cycle the MZ-80A. The system should boot and output video to the VGA monitor at the default resolution (640×480@60 Hz). Proceed to Using the Module — v2.0 to configure video modes and enable pixel graphics.
Firmware updates: When updated
.jic files are released, repeat steps 4–8 to re-programme the CPLD and FPGA. The MZ-80A does not need to be disassembled to update the firmware — the JTAG header is accessible from outside the case if the cable is routed during initial installation.
Using the Module — v1.x
40 / 80 Column Switching
Column mode is controlled by writing to the control latch at memory address
0xDFFF. Bit 7 selects the column width:
| Bit 7 | Mode |
|---|---|
| 0 | 40-column (default after power-on) |
| 1 | 80-column |
v1.0 (prototype): A direct byte write to
0xDFFF is sufficient.
v1.1 (current): A multivibrator on the board protects against spurious writes. The latch will only accept a new value if a read immediately precedes the write within a single instruction cycle. Use the following read-modify-write sequence:
; Switch to 80-column mode (v1.1) LD HL, 0xDFFF LD B, 0x80 ; bit 7 = 1 for 80-column LD A, (HL) ; read — triggers the multivibrator window LD (HL), B ; write within the window ; Switch to 40-column mode (v1.1) LD HL, 0xDFFF LD B, 0x00 ; bit 7 = 0 for 40-column LD A, (HL) ; read — triggers the multivibrator window LD (HL), B ; write within the window
Bits 1:0 of the latch byte select which group of four character sets is active (see Character ROM Selection). Always preserve these bits when switching column mode by reading the current latch value and ORing or ANDing only bit 7:
; Switch to 80-column preserving current CG-ROM group bits LD HL, 0xDFFF LD A, (HL) ; read current value (and trigger window) OR 0x80 ; set bit 7 only LD (HL), A ; write within the windowColour Output
The MZ-80A video hardware maintains a parallel attribute RAM at addresses
0xD800–0xDFFF (with the exception of the control latch at 0xDFFF itself). Each byte in attribute RAM corresponds to the same screen position as the character RAM byte at 0xD000–0xD7FF. The attribute byte encodes foreground colour, background colour, and character ROM sub-selection:
| Bits | Function |
|---|---|
| 2:0 | Background colour (bit 2 = Green, bit 1 = Red, bit 0 = Blue) |
| 3 | Character ROM selector bit 0 (sub-selects within the active group) |
| 6:4 | Foreground colour (bit 6 = Green, bit 5 = Red, bit 4 = Blue) |
| 7 | Character ROM selector bit 1 |
Colour values are formed by combining the three RGB bits. The eight possible colours are:
| RGB bits | Colour |
|---|---|
| 000 | Black |
| 001 | Blue |
| 010 | Red |
| 011 | Magenta |
| 100 | Green |
| 101 | Cyan |
| 110 | Yellow |
| 111 | White |
Example: Display the character 'A' at screen position (column 0, row 0) in blue on a black background:
; Character RAM and Attribute RAM both start at offset 0 for position (0,0) LD HL, 0xD000 LD (HL), 0x41 ; ASCII 'A' to character RAM LD HL, 0xD800 LD (HL), 0x10 ; foreground = blue (bit 4 set), background = black (bits 2:0 = 000)
Example: White characters on a blue background:
; Attribute byte: foreground white = 0x70 (bits 6:4 = 111), background blue = 0x01 (bits 2:0 = 001) ; Combined: 0x71 LD A, 0x71 LD (0xD800), A
To fill the entire screen with a single attribute value (e.g. white on black, 0x70) in a 40-column display (40×25 = 1000 character positions):
LD HL, 0xD800 LD BC, 0x03E8 ; 1000 = 40 columns × 25 rows LD A, 0x70 ; white foreground, black background FILL_LOOP: LD (HL), A INC HL DEC BC LD A, B OR C JR NZ, FILL_LOOPCharacter ROM Selection
The 32 KB Flash RAM installed at U10 holds up to 16 character sets (each 2 KB). The active character set for each screen position is selected by combining two sources of bits:
- Bits 1:0 of the control latch at
0xDFFF— select which group of four character sets (0–3) is active for the whole display. - Bits 7 and 3 of the attribute byte at the corresponding attribute RAM address — sub-select which of the four character sets within the active group is used for that individual character position.
COLOURBOARD_CG.rom image populates the slots as follows:
| Slot | Latch bits 1:0 | Attr bits 7, 3 | ROM image | Description |
|---|---|---|---|---|
| 0 | 00 | 0, 0 | mz-80acg | MZ-80A European character set |
| 1 | 00 | 0, 1 | MZ80K_cgrom | MZ-80K European character set |
| 2 | 00 | 1, 0 | MZ80K2E_Jap | MZ-80K Japanese character set |
| 3 | 00 | 1, 1 | MZFONT | Alternative font |
| 4 | 01 | 0, 0 | MZ700_cgrom (bank 0) | MZ-700 European (first 2 KB bank) |
| 5 | 01 | 0, 1 | MZ700_cgrom (bank 1) | MZ-700 European (second 2 KB bank) |
| 6 | 01 | 1, 0 | MZ700_cgrom_jp (bank 0) | MZ-700 Japanese (first 2 KB bank) |
| 7 | 01 | 1, 1 | MZ700_cgrom_jp (bank 1) | MZ-700 Japanese (second 2 KB bank) |
| 8 | 10 | 0, 0 | mz-80acg | MZ-80A European character set |
| 9 | 10 | 0, 1 | MZ80B | MZ-80B European character set |
| 10 | 10 | 1, 0 | mz-80acg | MZ-80A European (filler) |
| 11 | 10 | 1, 1 | mz-80acg | MZ-80A European (filler) |
| 12 | 11 | 0, 0 | mz-80acg | MZ-80A European (filler) |
| 13 | 11 | 0, 1 | mz-80acg | MZ-80A European (filler) |
| 14 | 11 | 1, 0 | mz-80acg | MZ-80A European (filler) |
| 15 | 11 | 1, 1 | mz-80acg | MZ-80A European (filler) |
Example: Select the MZ-80K European character set (slot 1) for all character positions. Set latch bits 1:0 to 00, and write attribute bytes with bit 3 set and bit 7 clear (value 0x08 ORed with your colour bits):
; Set latch: 80-column, CG group 0 (bits 1:0 = 00) LD HL, 0xDFFF LD A, (HL) AND 0xFC ; clear bits 1:0 OR 0x80 ; keep 80-column bit LD (HL), A ; Write attribute for MZ-80K European set, white on black ; attr bit 3 = 1, bit 7 = 0, foreground white (bits 6:4 = 111) = 0x78 LD A, 0x78 LD (0xD800), A ; apply to first character position
Custom character sets can be loaded into any of the 16 slots by programming the 28C256 Flash RAM with a modified image using the same 2 KB slot layout. See the project repository for the ROM image build scripts.
Using the Module — v2.0
The v2.0 FPGA-based Video Module is controlled entirely through Z80 I/O port writes. All v1.x functionality (40/80 column switching, colour attributes, CG-ROM selection) is available through the new register interface, and the original memory-mapped latch at
Control Register (I/O Port 0xF8)
0xDFFF continues to operate for backwards compatibility with v1.x software.
The primary control register is accessed via Z80
OUT (0xF8), A / IN A, (0xF8). It configures the emulated machine model, column width, colour mode, PCG RAM access, and VGA output resolution:
| Bits | Function |
|---|---|
| 2:0 | Machine model emulation |
| 3 | Column width: 0 = 40-column, 1 = 80-column |
| 4 | Colour mode: 0 = monochrome, 1 = colour |
| 5 | PCG RAM enable: 0 = disabled, 1 = enabled |
| 7:6 | VGA output mode |
Machine model values (bits 2:0):
| Value | Model |
|---|---|
| 000 | MZ-80K |
| 001 | MZ-80C |
| 010 | MZ-1200 |
| 011 | MZ-80A |
| 100 | MZ-700 |
| 101 | MZ-800 |
| 110 | MZ-80B |
| 111 | MZ-2000 |
VGA output mode values (bits 7:6):
| Value | Mode |
|---|---|
| 00 | Native — 15.62 kHz horizontal, 60 Hz vertical (original MZ-80A video timing) |
| 01 | 640×480 @ 60 Hz VGA |
| 10 | 1024×768 @ 60 Hz VGA |
| 11 | 800×600 @ 60 Hz VGA |
Example: Configure 80-column colour MZ-80A mode with 640×480 VGA output:
; Bits: VGA=01 (640x480), PCG=0, colour=1, 80col=1, model=011 (MZ-80A) ; Binary: 01 0 1 1 011 = 0x5B ... wait, let's build it: ; bits 7:6 = 01 (640x480) = 0x40 ; bit 5 = 0 (PCG off) = 0x00 ; bit 4 = 1 (colour) = 0x10 ; bit 3 = 1 (80-column) = 0x08 ; bits 2:0 = 011 (MZ-80A) = 0x03 ; Total: 0x40 | 0x10 | 0x08 | 0x03 = 0x5B LD A, 0x5B OUT (0xF8), A
Example: Switch to MZ-80B emulation with 800×600 VGA output, 80-column, monochrome:
; bits 7:6 = 11 (800x600) = 0xC0 ; bit 4 = 0 (mono) ; bit 3 = 1 (80-col) = 0x08 ; bits 2:0 = 110 (MZ-80B) = 0x06 ; Total: 0xC0 | 0x08 | 0x06 = 0xCE LD A, 0xCE OUT (0xF8), AVGA Output Modes
The FPGA scales the MZ-80A's native 40 or 80 column text display to the selected VGA resolution. All three VGA modes produce a correctly centred image with the MZ-80A character matrix scaled to fill the active display area. The native timing mode outputs the original 15.62 kHz video signal and is intended for period-correct monitors; most modern monitors will not sync to this signal.
The VGA border colour (the area outside the active character matrix) can be set independently using the border register:
; Set VGA border colour — I/O port 0xF3 ; Bits 2:0 = border RGB colour (same encoding as attribute colour bits) ; Example: blue border (RGB = 001) LD A, 0x01 OUT (0xF3), A ; Example: black border LD A, 0x00 OUT (0xF3), AGraphics Mode (I/O Port 0xF9)
The v2.0 Video Module includes a pixel graphics framebuffer providing 640×200 or 320×200 resolution with 8-colour output. The Graphics Mode Register at I/O port
0xF9 controls graphics RAM access, resolution, and how the graphics layer is composited over the text display:
| Bits | Function |
|---|---|
| 1:0 | Graphics RAM bank select (selects which 16 KB bank of graphics RAM is mapped for CPU access) |
| 2 | Graphics display enable: 0 = text only, 1 = graphics layer visible |
| 3 | Graphics resolution: 0 = 640×200 (8 colours), 1 = 320×200 (8 colours) |
| 4 | Blend mode: 0 = graphics overlays text (graphics pixels with colour 000/black are transparent), 1 = graphics only (text hidden) |
| 5 | Graphics RAM write-through: 0 = CPU reads/writes graphics RAM bank, 1 = CPU writes to both displayed and shadow banks |
The pixel framebuffer is mapped into CPU address space at
0xC000–0xFFFF (16 KB) when the PCG RAM enable bit in the Control Register (port 0xF8, bit 5) is set. Select the bank to expose using bits 1:0 of the Graphics Mode Register. At 640×200 with 3 bits per pixel, the full framebuffer requires three 16 KB banks.
Example: Enable 640×200 graphics overlay over the text display:
; Enable PCG RAM access in control register first IN A, (0xF8) OR 0x20 ; set bit 5 (PCG RAM enable) OUT (0xF8), A ; Configure graphics mode: bank 0, display enabled, 640x200, overlay blend ; bits 1:0 = 00 (bank 0), bit 2 = 1 (display on), bit 3 = 0 (640x200), bit 4 = 0 (overlay) LD A, 0x04 OUT (0xF9), A ; Graphics RAM is now accessible at 0xC000-0xFFFF ; Write pixel data...GPU Acceleration (I/O Ports 0xF6 / 0xF7)
The FPGA includes a simple GPU that can perform graphics operations (fills, block copies, line drawing) faster than the CPU can write pixels individually. Commands are issued by writing parameters to port
0xF6 and a command opcode to port 0xF7. Poll the busy bit (bit 7) of port 0xF7 to determine when the GPU has finished.
The general command sequence is:
; 1. Wait for GPU to be idle GPU_WAIT: IN A, (0xF7) BIT 7, A JR NZ, GPU_WAIT ; spin while busy (bit 7 = 1) ; 2. Write parameters to port 0xF6 (parameter format is command-specific) ; Example: write X coordinate low byte LD A, 0x00 OUT (0xF6), A ; Example: write X coordinate high byte LD A, 0x00 OUT (0xF6), A ; (continue writing all required parameters...) ; 3. Issue the command opcode to port 0xF7 LD A, CMD_FILL ; replace CMD_FILL with the appropriate opcode OUT (0xF7), A ; 4. Optionally wait for completion before relying on the result GPU_DONE: IN A, (0xF7) BIT 7, A JR NZ, GPU_DONE
Full GPU command opcodes, parameter sequences, and worked examples are documented in the Video Module Technical Reference available in the project repository under
docs/.
Troubleshooting
MZ-80A will not boot after installing the Video Module
- Raiser pins not fully seated — power off and press the daughter board firmly down onto all three DIP sockets. Check that no pins are bent or missing the socket holes.
- Solder bridge on a DIP socket — inspect the motherboard socket solder joints under magnification. A bridge between adjacent pins on IC8, IC9, or IC15 sockets will cause a bus conflict.
- Ribbon cable reversed — the 34-pin ribbon cable must have pin 1 (red stripe) aligned with the pin 1 marker on both the daughter board and the motherboard Video expansion connector. Reversing the cable will drive the video bus with incorrect signals.
- CG-ROM not inserted — the 28C256 Flash RAM must be installed in U10. Without it the character generator output is undefined and the display will appear as random noise or fail to sync.
- CG-ROM incorrectly programmed — verify the Flash RAM contains
COLOURBOARD_CG.romusing the programmer's verify function before installation.
MZ-80A boots but no image appears on the colour monitor
- Wrong monitor input selected — ensure the monitor's input is set to RGB or composite as appropriate for the output connector you are using.
- Output connector not routed correctly — verify the RGB / composite output connector is securely connected to J2 on the daughter board and that the external connector is correctly wired.
- Monitor does not support 15.62 kHz horizontal sync — the v1.1 board outputs the MZ-80A's native video timing. Many modern monitors will not sync to 15.62 kHz. Use a period-correct monitor, a SCART-equipped CRT, or a scan doubler / upscaler.
80-column mode does not activate (v1.1)
- Using a direct write without the read-modify-write sequence — v1.1 requires a read from
0xDFFFimmediately before the write. A directLD (0xDFFF), Awithout the preceding read will be rejected by the multivibrator protection circuit. Use the sequence shown in 40 / 80 Column Switching. - v1.0 board — if this is a v1.0 prototype board, the multivibrator protection is absent and a direct write should work. If it does not, the board may have one of the five known v1.0 hardware defects. Contact the project page.
- Interrupts enabled during the write sequence — on a system with active interrupts, an interrupt service routine could execute between the read and the write, collapsing the multivibrator window. Disable interrupts (
DI) around the read-write pair and re-enable them (EI) afterwards.
Colours are incorrect or characters appear in wrong character sets
- Attribute RAM not initialised — after power-on the attribute RAM contents are undefined. Initialise the attribute RAM to the desired default value (typically 0x70 for white-on-black using the MZ-80A character set) before displaying content.
- CG-ROM selector bits in attribute bytes not as expected — bits 7 and 3 of each attribute byte contribute to character set selection as well as colour. A program that does not use the Video Module may write attribute bytes without regard to bits 7 and 3, causing unexpected character set selection. Mask these bits explicitly in your attribute writes.
- Latch bits 1:0 not set correctly — if the wrong CG group is active, all character positions will draw from an unexpected group of four character sets regardless of the attribute bits. Read the latch value and verify bits 1:0 match your intended group.
No VGA output from v2.0 board
- CPLD or FPGA not programmed — both devices must be programmed via JTAG before the board will produce any output. If either programming step failed or was skipped, repeat the programming procedure from Installing the Video Module v2.0.
- tranZPUter not correctly interfacing — verify the tranZPUter board is functioning correctly independently before troubleshooting the Video Module. If the MZ-80A does not boot with the tranZPUter alone, resolve that first.
- VGA mode set to native timing — bits 7:6 of port 0xF8 set to 00 selects the native 15.62 kHz output, which most VGA monitors will not display. Write bits 7:6 = 01 (640×480) to select a standard VGA mode.
- Incorrect Quartus version used — the CPLD and FPGA require different Quartus Prime versions. Using 13.1 to program the CPLD (which requires 13.0.1) or vice versa may produce a valid-looking but non-functional bitstream. Use the correct version for each device.
Known v1.0 Prototype Errata
The v1.0 prototype board has five documented hardware defects corrected in v1.1. The v1.0 board is not recommended for general use. If you have a v1.0 board, contact the project page for details of the specific errata and for information on obtaining a v1.1 replacement PCB.
Reference Sites
| Resource | Link |
|---|---|
| Video Module project page | /sharpmz-upgrades-videomodule/ |
| Video Module Technical Reference | Available in repository docs/ directory |
| tranZPUter project page | /sharpmz-upgrades-tranzputer/ |
| RFS User Manual | /sharpmz-upgrades-rfs-usermanual/ |
| Sharp MZ-80A Service Manual | Available from archive.org and Sharp documentation archives |
| Quartus Prime 13.0.1 (CPLD) | Intel FPGA Download Center |
| Quartus Prime 13.1 (FPGA) | Intel FPGA Download Center |
| minipro programmer utility | https://gitlab.com/DavidGriffith/minipro |