tranZPUter SW-700 — Technical Guide

tranZPUter SW-700 Technical Guide (Current Version)

This guide documents the hardware architecture, bus-mastering mechanism, memory management modes, system registers, K64F service API, CPU switching, video module, FPGA specifications, and build system for the current version of the tranZPUter SW-700 — the expansion board that adds a K64F I/O processor, a CPLD, and an Altera FPGA to the Sharp MZ-700 (and, in the current version, the Sharp MZ-2000).

The current version supports MZ-2000 hardware emulation and uses larger FPGA devices (Cyclone IV EP4CE75 or EP4CE115) compared to the v1.2 baseline (Cyclone III EP3C25). Everything in this guide applies to the current hardware unless a version qualifier (v1.2 / v1.3) is explicitly stated.

For day-to-day usage and TZFS command reference see the User Manual. For Z80 assembly and FPGA source walkthroughs see the Developer's Guide.

Bus Mastering

The tranZPUter SW-700 plugs into the Sharp MZ-700 (or MZ-2000) expansion bus. Its CPLD monitors the bus and can assert the Z80 /BUSRQ line at any time. When /BUSRQ is asserted the Z80 completes its current machine cycle and then tri-states its address, data, and control buses, signalling bus release via /BUSAK.

Once the Z80 releases the bus, the FPGA takes ownership of all three buses. In this state the FPGA can act as:

A DMA engine — bulk-transferring data between the 512 KB SRAM and main board memory without Z80 involvement.

A soft CPU — the T80 or ZPU Evolution cores execute directly from the SRAM, addressing the full memory space as if they were the system CPU.

When the FPGA releases /BUSRQ the Z80 reclaims its buses and resumes execution from exactly the point it was suspended — all register state is preserved because the Z80 was never reset. The SRAM contents are also preserved across the handoff, so code or data placed there by the FPGA remains available to Z80 programs.

The CPLD handles level translation between the 5 V MZ bus signals and the 3.3 V FPGA I/O, and performs address decode so that tranZPUter registers appear in the Z80 I/O space without conflicting with MZ mainboard peripherals.

Hardware Components

K64F ARM Cortex-M4 (I/O Processor)

The NXP/Freescale K64F runs at 120 MHz and acts as the system's I/O processor. It operates independently of the Z80 and FPGA, running the zOS embedded operating system. Its responsibilities are:

SD card management — provides FAT32 file system access to the SD card. All MZF program files, ROM images, and FPGA bitstreams are stored here.

Firmware / ROM loading — reads ROM images and FPGA bitstreams from the SD card and loads them into the 512 KB SRAM or into FPGA configuration flash.

TZFS service API — handles requests from Z80 programs running under TZFS (tranZPUter Filing System). The Z80 writes a command and parameters into a shared memory region at 0xED80, then triggers the K64F via the SVCREQ register at I/O port 0x68. The K64F polls for the request, executes it, writes results back into shared memory, and clears the SVCREQ flag.

CPU frequency synthesis — generates an alternate CPU clock that can be switched to the Z80 on demand, enabling the Z80 to run at speeds other than the MZ mainboard's native frequency.

The K64F connects to the FPGA and CPLD over dedicated control lines and shares the SRAM bus with the FPGA.

MAX 7000A CPLD (512 Macro Cells)

The Altera MAX 7000A is a 5 V tolerant CPLD with 512 macro cells. It sits directly on the MZ expansion bus and performs three functions:

Level translation — bridges 5 V MZ-700/MZ-2000 bus signals to the 3.3 V FPGA I/O rails.

Bus mastering logic — asserts /BUSRQ to the Z80 and monitors /BUSAK to arbitrate bus ownership between the Z80 and FPGA.

Address decode — maps tranZPUter I/O registers (0x60–0x6F, 0xA8–0xAD, 0xF0, etc.) into the Z80 I/O space and gates SRAM into the Z80 address space according to the active TZMM memory management mode.

Altera FPGA

Two FPGA variants are used across board revisions:

Version	Device	Logic Elements	BRAM	Package
v1.2	Cyclone III EP3C25E144C8	25K LE	76 KB	144-pin TQFP
v1.3	Cyclone IV EP4CE75F484C8	75K LE	360 KB	484-pin BGA
v1.3	Cyclone IV EP4CE115F484C8	115K LE	480 KB	484-pin BGA

The FPGA implements:

T80 soft Z80 — a synthesised Z80-compatible CPU that takes over the buses when bus mastering is active.

ZPU Evolution soft CPU — a 32-bit stack-based soft processor that can execute ZPU binaries from SRAM.

Video controller — supports all Sharp MZ video modes and provides VGA output (see Video Module).

GPU — hardware-accelerated graphics primitives (VRAM clear, rectangle fill, GRAM clear).

The FPGA configuration is stored in SPI Flash: EPCS16 (v1.2) or EPCS64 (v1.3). The K64F can reprogram this flash from a bitstream on the SD card.

512 KB Static RAM (AS6C4008)

A single 512 KB × 8 AS6C4008 SRAM device provides the tranZPUter's expanded memory. The CPLD pages different regions of this SRAM into the Z80's 64 KB address space depending on the active TZMM mode (see Memory Management Modes). The SRAM is accessible to both the Z80 (via the CPLD address decoder) and the FPGA (via direct connection), and its contents persist across bus-mastering handoffs.

Power Supplies

Three on-board LDO regulators derive the required supply rails from the MZ expansion bus 5 V supply:

Rail	Consumers
3.3 V	CPLD, K64F, general I/O, SRAM
2.5 V	FPGA I/O banks
1.2 V	FPGA core

Memory Management Modes

The CPLD implements a memory management unit controlled by writing a mode value to I/O port 0x60. Each mode selects how regions of the 512 KB SRAM are paged into the Z80's 64 KB address space, and whether the MZ mainboard ROM and RAM or the tranZPUter SRAM services each address range.

The mode register is referred to as the TZMM (tranZPUter Memory Mode) register. Key modes are:

Mode	Value	Description
TZMM_ORIG	0x00	Original MZ-700 mode — mainboard IPL ROM, DRAM, and VRAM visible as normal. tranZPUter SRAM inactive.
TZMM_BOOT	0x01	tranZPUter SRAM mapped at 0xE800–0xEFFF to hold the TZFS bootstrap. All other addresses use mainboard resources.
TZMM_TZFS	0x22	TZFS mode — entire 64 KB address space served from tranZPUter SRAM. The K64F has preloaded TZFS code and ROM images.
TZMM_TZFS2	0x23	TZFS banked mode — alternate code bank 2 active.
TZMM_TZFS3	0x24	TZFS banked mode — alternate code bank 3 active.
TZMM_TZFS4	0x25	TZFS banked mode — alternate code bank 4 active.
TZMM_CPM	0x26	CP/M mode — full 64 KB SRAM mapped, CBIOS and CCP loaded by K64F.
TZMM_CPM2	0x27	CP/M mode variant — alternate CBIOS bank active.
TZMM_MZ700_0	—	MZ-700 compatibility paging — mainboard ROM and VRAM layout preserved.
TZMM_MZ2000	—	MZ-2000 compatibility paging — MZ-2000 ROM and VRAM layout emulated. Current version only.

On power-on the CPLD starts in TZMM_ORIG (0x00), presenting the standard MZ-700 memory map. The TZFS bootstrap ROM at 0xE800 switches to TZMM_BOOT to make itself visible, then switches to TZMM_TZFS once the K64F has loaded the full TZFS image into SRAM.

TZMM_ORIG (0x00) — Original MZ-700 layout
  0x0000–0x0FFF   MZ mainboard IPL ROM
  0x1000–0xCFFF   MZ mainboard DRAM
  0xD000–0xDFFF   MZ mainboard VRAM / memory-mapped I/O
  0xE000–0xE7FF   MZ mainboard VRAM extension / I/O
  0xE800–0xEFFF   MZ mainboard ROM (User ROM area)
  0xF000–0xFFFF   MZ mainboard ROM / unused

TZMM_TZFS (0x22) — Full SRAM mode
  0x0000–0xFFFF   tranZPUter 512 KB SRAM (64 KB window)
                  K64F has loaded: IPL at 0x0000, TZFS at 0xE800, ROMs throughout

TZMM_CPM (0x26) — CP/M mode
  0x0000–0xFFFF   tranZPUter 512 KB SRAM (64 KB window)
                  K64F has loaded: CP/M CCP+BDOS+CBIOS

System Registers

The tranZPUter maps its control registers into the Z80 I/O address space. All registers are accessed with Z80 IN and OUT instructions. The CPLD decodes the I/O addresses and routes accesses to the appropriate hardware.

Port    Register                     R/W   Description
──────────────────────────────────────────────────────────────────────────────
0x60    Memory Management Config      W    TZMM mode select (see Memory Modes)
0x62    Set CPU Alt Frequency         W    Switch Z80 clock to K64F-generated alternate frequency
0x64    Set CPU Base Frequency        W    Switch Z80 clock back to MZ mainboard frequency
0x66    CPU Frequency Change          W    Set exact CPU frequency in Hz (32-bit value via shared mem)
0x68    Service Request (SVCREQ)      W    Trigger K64F service request; K64F polls and clears on completion
0x6B    System Command Register       W    System-level commands (reset, mode changes)
0x6C    CPU Configuration             R/W  Select active CPU core (Z80, T80, ZPU Evolution)
0x6D    CPU Information               R    Read available CPU capabilities and soft-CPU presence
0x6E    System Configuration          R/W  System feature flags
0x6F    System Information            R    Board identification and hardware status
0xA8    Video Control                 R/W  Machine model, column width, colour enable, PCG, VGA mode
0xA9    Video Graphics Mode           R/W  GRAM bank select, VRAM/GRAM output enable, blend operator
0xAA    Colour Writer Red             W    8-pixel red channel filter mask for indirect GRAM writes
0xAB    Colour Writer Green           W    8-pixel green channel filter mask for indirect GRAM writes
0xAC    Colour Writer Blue            W    8-pixel blue channel filter mask for indirect GRAM writes
0xAD    Memory Page / Status          R/W  GRAM→CPU enable (W bit 0), CGROM→CPU enable (W bit 7);
                                          H/V blanking status (R bits 5–6)
0xD0    Video Mode Parameter 0        R/W  Video timing / mode parameter
0xD1    Video Mode Parameter 1        R/W  Video timing / mode parameter
0xD2    Video Mode Parameter 2        R/W  Video timing / mode parameter
0xD3    Palette Entry 0               W    Palette colour data
0xD4    Palette Entry 1               W    Palette colour data
0xD5    Palette Entry 2               W    Palette colour data
0xD6    Palette Entry 3               W    Palette colour data
0xD7    Palette Entry 4               W    Palette colour data
0xF0    System Control (CPLD)         W    CPLD direct control register
0xF3    VGA Border Colour             W    Border colour for VGA output
0xF5    Palette Select                W    Select active palette entry for subsequent palette writes
?F6     GPU Parameters                W    Parameters for GPU primitive commands
?F7     GPU Command / Status          R/W  Issue GPU command (W); read GPU busy/done status (R)
──────────────────────────────────────────────────────────────────────────────

CPU Configuration Register — Port 0x6C

Bits	Field	Description
2:0	CPU Select	000 = Z80 (hard CPU on mainboard), 001 = T80 (soft Z80 in FPGA), 010 = ZPU Evolution (soft 32-bit CPU in FPGA), 011–111 = reserved
7:3	—	Reserved, write zero

CPU Information Register — Port 0x6D (read)

Bits	Field	Description
2:0	CPUMODE_IS_SOFT_MASK / CPUMODE_IS_SOFT_AVAIL	Non-zero if one or more FPGA soft CPU cores are available in the current bitstream
3	CPUMODE_IS_T80	Set if the T80 soft Z80 core is present
4	CPUMODE_IS_ZPU_EVO	Set if the ZPU Evolution core is present
5	CPUMODE_IS_EMU_MZ	Set if machine emulation (MZ model switching) is available
7:6	—	Reserved

K64F Service API

The K64F exposes a service API to Z80 programs running under TZFS. The mechanism is a shared memory region in SRAM — the Z80 writes a command and any parameters into the region, triggers the K64F, and polls for completion. No bus mastering is required; the Z80 and K64F communicate through ordinary memory reads and writes while the K64F monitors the SVCREQ register.

Request / Response Mechanism

Shared memory base: 0xED80 (in SRAM, visible to Z80 in TZMM_TZFS and related modes)

Offset  Symbol        Description
──────────────────────────────────────────────────────────────
0x00    TZSVCCMD      Service command code (1 byte, written by Z80)
0x01    TZSVCSTS      Status / result code (1 byte, written by K64F on completion)
0x02    TZSVCREQ      Request semaphore (set by Z80, cleared by K64F)
0x04    TZSVCP1       Parameter 1 (command-specific)
...     ...           Parameters 2–N (command-specific sizes and meanings)
──────────────────────────────────────────────────────────────

Z80 procedure:
  1. Write command code to TZSVCCMD (0xED80).
  2. Write parameters to TZSVCP1 onwards.
  3. OUT (0x68), A          ; assert SVCREQ — wakes K64F
  4. Poll TZSVCSTS until non-zero (K64F has completed the request).
  5. Read result data from shared memory.

Service Command Reference

The following table lists key service commands. Parameter details are documented in the TZFS firmware source.

Command	Category	Description
READDIR	File I/O	Read directory entries from the SD card FAT32 volume
LOADFILE	File I/O	Load a named file from SD card into SRAM
SAVEFILE	File I/O	Save a region of SRAM as a named file on SD card
LOAD40ABIOS	BIOS Load	Load MZ-80A BIOS ROM image into SRAM
LOAD700BIOS40	BIOS Load	Load MZ-700 40-column BIOS image into SRAM
LOAD2000IPL	BIOS Load	Load MZ-2000 IPL ROM image into SRAM (current version only)
ADDSDDRIVE	CP/M Disk	Register an SD card CP/M disk image
READSDDRIVE	CP/M Disk	Read a 128-byte CP/M sector from an SD card disk image
WRITESDDRIVE	CP/M Disk	Write a 128-byte CP/M sector to an SD card disk image
CPU_BASEFREQ	CPU Freq	Switch Z80 clock to MZ mainboard native frequency
CPU_ALTFREQ	CPU Freq	Switch Z80 clock to K64F-generated alternate frequency
CPU_CHGFREQ	CPU Freq	Set Z80 clock to a specific frequency in Hz
CPU_SETZ80	CPU Switch	Activate the physical Z80 (release bus mastering)
CPU_SETT80	CPU Switch	Load T80 firmware and activate the T80 soft Z80 in FPGA
CPU_SETZPUEVO	CPU Switch	Load ZPU Evolution firmware and activate the ZPU soft CPU
EMU_SETMZ80K	Emulation	Configure FPGA video and I/O to emulate MZ-80K
EMU_SETMZ80C	Emulation	Configure FPGA to emulate MZ-80C
EMU_SETMZ1200	Emulation	Configure FPGA to emulate MZ-1200
EMU_SETMZ80A	Emulation	Configure FPGA to emulate MZ-80A
EMU_SETMZ700	Emulation	Configure FPGA to emulate MZ-700
EMU_SETMZ800	Emulation	Configure FPGA to emulate MZ-800
EMU_SETMZ80B	Emulation	Configure FPGA to emulate MZ-80B
EMU_SETMZ2000	Emulation	Configure FPGA to emulate MZ-2000 (current version only)
EMU_SETMZ2500	Emulation	Configure FPGA to emulate MZ-2500

CPU Switching

The tranZPUter can operate with three CPU choices: the physical Z80 on the MZ mainboard, the T80 soft Z80 implemented in the FPGA, and the ZPU Evolution 32-bit soft CPU implemented in the FPGA. CPU switching is coordinated between the Z80 program, the K64F, and the FPGA.

Switching Procedure

The Z80 program issues a CPU_SETT80 or CPU_SETZPUEVO service request via the K64F API (port 0x68).

The K64F loads the required firmware image for the target CPU from the SD card into the 512 KB SRAM.

The K64F signals the FPGA to activate the new CPU core. The CPLD asserts /BUSRQ to the Z80.

Once the Z80 releases the bus (/BUSAK asserted), the FPGA soft CPU takes ownership of the address, data, and control buses and begins executing from the SRAM.

The physical Z80 remains held in bus-released state for the duration of soft CPU execution.

To return to Z80 execution, the running program (or the K64F) issues CPU_SETZ80, which causes the FPGA to release /BUSRQ. The Z80 reclaims its buses and resumes. SRAM contents are preserved.

The CPU Configuration Register at I/O port 0x6C can also be written directly to select a CPU core; writing this register triggers the same K64F coordination flow.

Available CPU Cores

Core	Port 0x6C bits 2:0	Notes
Z80 (hard)	000	Physical Z80 on MZ mainboard. Default after reset.
T80	001	Synthesised Z80-compatible core in FPGA fabric. Full Z80 instruction set.
ZPU Evolution	010	32-bit stack-based soft CPU in FPGA. Executes ZPU binaries.
Reserved	011–111	Not currently assigned.

The CPU Information Register (0x6D) should be read before attempting a CPU switch to confirm the desired core is present in the loaded FPGA bitstream. The CPUMODE_IS_T80 (bit 3) and CPUMODE_IS_ZPU_EVO (bit 4) flags indicate availability.

Video Module

The FPGA implements a complete video controller supporting all Sharp MZ display modes and adding a graphics framebuffer with VGA output. Video registers are mapped into the Z80 I/O space at 0xA8–0xAD (primary control), with additional registers at 0xD0–0xD7 (palette and mode parameters) and 0xF3, 0xF5 (VGA border and palette select).

In the current version, support for MZ-2000 video hardware is included alongside all previously supported MZ models.

Primary Video Registers (0xA8–0xAD)

Port 0xA8 — Video Control Register
  Bits 2:0   Machine model select
               000 = MZ-80K
               001 = MZ-80C
               010 = MZ-1200
               011 = MZ-80A
               100 = MZ-700
               101 = MZ-800
               110 = MZ-80B
               111 = MZ-2000  (current version only)
  Bit  3     Column width: 0 = 40 columns, 1 = 80 columns
  Bit  4     Colour enable: 0 = monochrome, 1 = colour
  Bit  5     PCG (Programmable Character Generator) enable
  Bits 7:6   VGA output mode:
               00 = 640×480 @ 60 Hz
               01 = 800×600 @ 60 Hz
               10 = 1024×768 @ 60 Hz
               11 = reserved

Port 0xA9 — Graphics Mode Register
  Bits 1:0   GRAM bank select (selects which of the three R/G/B banks is the active write target)
  Bit  2     VRAM output enable
  Bit  3     GRAM output enable
  Bits 5:4   Blend operator (OR, AND, XOR, REPLACE)
  Bits 7:6   Reserved

Port 0xAA — Colour Writer Red Filter
  Bits 7:0   8-pixel red channel mask for indirect (colour-writer) GRAM writes
             Each bit corresponds to one pixel in a horizontal 8-pixel stripe

Port 0xAB — Colour Writer Green Filter
  Bits 7:0   8-pixel green channel mask (same pixel layout as 0xAA)

Port 0xAC — Colour Writer Blue Filter
  Bits 7:0   8-pixel blue channel mask (same pixel layout as 0xAA)

Port 0xAD — Memory Page / Status Register
  Write:
    Bit  0   GRAM→CPU enable: 1 = map GRAM into CPU address space for direct read/write
    Bit  7   CGROM→CPU enable: 1 = map Character Generator ROM into CPU address space
  Read:
    Bit  5   Horizontal blanking status: 1 = currently in HBlank
    Bit  6   Vertical blanking status:   1 = currently in VBlank

Graphics Framebuffer

The FPGA implements a 640×200 (or 320×200) graphics layer alongside the character display. The framebuffer is organised as three independent 16 KB banks — Red, Green, and Blue — giving 3-bit (8-colour) pixel data. Each bank is 1 bit per pixel at 640×200.

Writes to the GRAM can be performed in two ways:

Direct mode — set GRAM→CPU enable (port 0xAD bit 0), then read or write GRAM addresses directly from Z80 code. Each bank is individually selected via port 0xA9 bits 1:0.

Colour writer mode — write once to the VRAM character address; the colour writer hardware simultaneously updates all three GRAM banks using the 8-pixel masks written to ports 0xAA, 0xAB, 0xAC. This allows a single write to paint a coloured character cell.

VGA Output

The FPGA scales the native Sharp MZ display to standard VGA timings. Three output resolutions are selectable via port 0xA8 bits 7:6. On v1.3 hardware, double-buffered display is available in all modes — the display reads from one buffer while the Z80 or GPU writes to the other.

VGA Mode (bits 7:6)	Output Resolution	Refresh
00	640 × 480	60 Hz
01	800 × 600	60 Hz
10	1024 × 768	60 Hz
11	Reserved	—

GPU

A simple GPU is accessible via I/O ports ?F6 (parameters) and ?F7 (command/status). Supported primitives:

Clear VRAM — fill the character display with a specified character and attribute.

Fill Rectangle — fill a rectangular region of GRAM with a colour.

Clear GRAM — zero all three GRAM banks.

Writing a command code to ?F7 starts the operation. Reading ?F7 returns a busy/done status flag. The Z80 should poll the status flag before issuing the next command.

FPGA Specifications

Full capability summary for each FPGA variant used on the tranZPUter SW-700:

Feature	v1.2 (EP3C25)	v1.3 (EP4CE75 / EP4CE115)
Logic elements	25K	75K / 115K
On-chip BRAM	76 KB	360 KB / 480 KB
Package	144-pin TQFP	484-pin BGA
Configuration flash	EPCS16	EPCS64
Soft CPUs	T80, ZPU Evolution	T80, ZPU Evolution
MZ video models	MZ-80K/C/1200/80A/700/800/80B	+ MZ-2000 (current)
VGA output	640×480, 800×600, 1024×768	640×480, 800×600, 1024×768
Double-buffered display	No	Yes (all modes)
GRAM banks	3 × 16 KB (R/G/B)	3 × 16 KB (R/G/B)
GPU	Clear VRAM, fill rect, clear GRAM	Clear VRAM, fill rect, clear GRAM

Supported MZ video modes (current version FPGA):
  MZ-80K    — 40×25 monochrome character display
  MZ-80C    — 40×25 monochrome character display
  MZ-1200   — 40×25 monochrome character display
  MZ-80A    — 40×25 monochrome character display
  MZ-700    — 40×25 character display with 8-colour attribute
  MZ-800    — 40×25 / 80×25 character; 320×200 / 640×200 graphics
  MZ-80B    — 40×25 character display; 320×200 / 640×200 graphics
  MZ-2000   — 40×25 / 80×25 character; 320×200 / 640×200 graphics (current version only)

Graphics framebuffer:
  Resolution: 640×200 or 320×200 pixels
  Colour depth: 3 bits per pixel (8 colours)
  Organisation: 3 independent 16 KB planes — Red, Green, Blue
  Total GRAM: 3 × 16 KB = 48 KB

Build System

The tranZPUter SW-700 firmware spans three components, each with its own toolchain: FPGA bitstream (Quartus Prime), K64F firmware (ARM GCC), and Z80 software (GLASS assembler). All development is done under Linux.

FPGA — Quartus Prime

The FPGA RTL is synthesised with Altera/Intel Quartus Prime. The required version depends on the target device:

Board Version	FPGA Device	Quartus Version
v1.2	Cyclone III EP3C25	13.1 (last version with Cyclone III support)
v1.3	Cyclone IV EP4CE75 / EP4CE115	Current Quartus Prime Lite / Standard

Docker containers are provided in the repository to reproduce the exact build environment for each version, avoiding toolchain installation on the development host. Run the appropriate container, then use the standard Quartus build flow (quartus_sh --flow compile) or open the project in the Quartus GUI.

After synthesis, the generated .sof (SRAM Object File) or .rbf (Raw Binary File) is written to the EPCS flash using the Quartus Programmer, or can be placed on the SD card for the K64F to load at boot time.

K64F Firmware — ARM GCC

The K64F firmware (zOS) is built with the ARM bare-metal GCC toolchain (arm-none-eabi-gcc). The build entry point is buildhost.sh located under software.moved.to.TZFS/:

cd software.moved.to.TZFS
./buildhost.sh

The script compiles the zOS kernel, the SD card FAT32 driver, the SVCREQ service dispatch table, and all supporting I/O drivers, then links and produces a binary suitable for flashing to the K64F. Flashing is performed via the K64F's USB DFU bootloader (drag-and-drop to the mass-storage device that appears when the K64F boots into DFU mode).

Z80 / TZFS Software — GLASS Assembler

TZFS and related Z80 software are assembled with the GLASS Z80 assembler (bundled as tools/glass.jar, requires Java 8+). Build scripts in the software.moved.to.TZFS/ tree invoke GLASS and package the resulting binaries as MZF images for the SD card.

Reference Sites

Resource	Link
tranZPUter SW-700 project page	/sharpmz-upgrades-tranzputer-sw700/
tranZPUter SW-700 User Manual	/sharpmz-upgrades-tranzputer-sw700-usermanual/
tranZPUter SW-700 Developer’s Guide	/sharpmz-upgrades-tranzputer-sw700-developersguide/
tranZPUter SW-700 Gallery	/sharpmz-upgrades-tranzputer-sw700-gallery/
RFS Technical Guide	/sharpmz-upgrades-rfs-technicalguide/
Sharp MZ-700 hardware reference	MZ-700 Technical Manual
Altera MAX 7000A datasheet	Intel/Altera MAX 7000A product page
NXP K64F Sub-Family Reference	NXP K64 Reference Manual
GLASS Z80 Assembler	Bundled in `tools/glass.jar`
Quartus Prime (Intel FPGA)	https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html