Projects advancing…

2 minute read

Like most of Europe, many are forced to stay at home for the next few weeks, so rather than go mad, time to forward all the on-going projects.

Rom Filing System

I have made quite a headway on the Rom Filing System, adding an SD Card and CP/M v2.23, the Sharp MZ80A is now all the machine I wanted it to be 20+ years ago. Still more edges to round on the design and software, but it is getting nearer to completion.


Some strange behaviour during testing led me to fry U9 as I was probing the signals with my oscilloscope. The pins are so tiny and working after midnight is probably not a good idea, so a tricky job replacing it. Also there were some hardware bugs in the addressing and latching of the 2 16bit latches CY74FCT16543T which needed board modifications. The schematics have been updated with the changes.

Now currently working on the Finite State Machines in VHDL to perform accurate Z80 Read/Write cycles in order that a soft-cpu or ZPU Evo can control the MZ80A Host hardware.


After quite sometime perfecting the SDRAM, both vanilla and cached versions, and running numerous tests where the memory passed with flying colours at 100MHz, I decided to try it out on the Trenz Electronic CYC1000 in the tranZPUter which went well until I ran a ZPUTA application! Some of the smaller apps ran fine but others just went haywire. After many hours of debugging and pondering, I came to the logical conclusion, which I proved, that the L2 to L1 cache mechanism had a timing flaw when dealing with the SDRAM and it’s timing uncertainty. When a ZPU Jump intruction was encountered which jumped out of scope of L2, the L1 and L2 caches were flushed and L2 began to fetch new data from SDRAM. The CPU was held in a wait state and once data was in L2 it began to trickle into L1 and the CPU allowed to continue. Between the L2 filling and the L1 obtaining its first word from L2, a timing bug occurs and L1 receives data from L2 which belonged to the pre-flushed cache set. If I slow the CPU down by adding wait states, it works fine but at full speed this bug just rears its ugly head. After many a late night debugging and pondering, I decided to take a break and work on some of the other projects, coming back to this issue later with fresh eyes! To quote an old saying, ‘So close, yet so far!!’