This is a collection of projects that I am currently working on in my spare time, being educated in microelectronics I like to keep active in this field even though my bread and butter work tends to be software development in real time financial trading markets.
The documentation on this site tends to start off as an information dump and then over time will become more professional and complete.
All of these projects are made open source so feel free to collaborate, fork or add issues.
Current activity: tranZPUter SW
|tranZPUterSW||26/06/20||Design updated to v1.1 and new PCB designed and ordered. V2.0 is under way using a CPLD to decrease size and add ability to easily add required features (such as MZ80B virtual hardware).|
|18/06/20||Hardware updated to support WAIT state generation on IO commands. This now allows the MZ-700 software such as S-BASIC to run. Added Microsoft (NASCOM) Basic in two flavours, original MZ-80A and tranZPUter variants with updated commands to access the SD card and a converter program to convert NASCOM tape images. Star Trek V2 running at 10MHz under Microsoft BASIC with the inbuilt ANSI Terminal Emulator is now much more playable.|
|10/06/20||MZ-700 mode needs hardware assistance on memory bank switching, even over clocking the K64F at 168MHz it still misses the odd Z80 IORQ timing requirement due to other IRQ events such as the thread library. Patched the 1Z-013A MZ-700 BIOS to use the MZ80A keyboard and adjusted the colour attribute RAM, so almost ready to run MZ-700 software on the tranZPUterSW.
Completed the multi-frequency option for the Z80, it now clocks at 9MHz reliably on the Z80H CPU which makes CP/M fly!!
|07/06/20||Adding the MZ700 mode is proving more tricky, written ARM assembly ISR routines but the K64F isnt as fast as I had presumed. Example, highest priority interrupt on IORQ with just two register pushes and a bit toggle only just meet the Z80 timing to add a wait state. WIP!! Documentation slowly being updated.|
|04/06/20||TZFS written (TranZputer Filing System) and CP/M ported and CBIOS written, result is actually better than the MZ80A_RFS and more developments planned. Documentation to be updated shortly.|
|19/05/20||Development underway, tools written to create the decoder flashram map, tools written for zOS, can load, save and manipulate all the memory on the tranZPUter SW board and on the Sharp MZ80A host from zOS, base library coded for K64F access to the Z80 host and tranZPUter board in C|
|13/05/20||tranZPUter SW v1.0 PCB fully assembled and tested. Software development now underway.|
|09/04/20||Parallel project to the tranZPUter, designed the hardware and PCB, readying zOS to use with this project.|
|zSoft||18/06/20||*Further updates for NASCOM BASIC and the MZ-700 mode with the new hardware**|
|10/06/20||Further updates to accommodate TZFS, CP/M and MZ-700 mode running on the tranZPUter SW board with multi-frequency switching.|
|19/05/20||Bug fixes to zOS as it gets used for the tranZPUter SW project. Tools and libraries written for the tranZPUter SW to utilise the new board and to provide a platform to port RFS to the tranZPUter.|
|12/05/20||Major changes. I decided to adopt more standard C Libraries especially as the K64F ARM compiler and libraries were difficult to use without libc, so I’ve added umlibc for the ZPU and removed the El Chan xprintf library. Also standardised memory management, the OS manages its heap and applications generally call on the OS for memory allocation but Ive kept in place the framework for an application to have its own memory management if needed.|
|28/04/20||Merged IOCP, ZPUTA, zOS and Applications from ZPU Evo and tranZPUter repositories. All software for the two projects will be made in this repo.|
|MZ80A RFS||14/05/20||New PCB assembled, tested and the RFS and CPM CBIOS software updated. The Hardware SPI gives almost Flash RAM performance and is ideal for CPM use. A minor tweak to the hardware was needed due to the CSUSR signal being activated as an artifact of the 82S100N configuration on the main motherboard and R2 was removed given the choice of XTAL, but otherwise all as designed.|
|02/04/20||New version of the hardware and PCB design based on enhancement of the shortcomings of version 1.1. v2.0 schematic , v2.0 pcb.|
|24/03/20||More major changes, added an SD card to the design, updated the RFS to access Sharp MZ80A programs on the SD card and also updated CPM so that it can access the SD card as a set of virtual 16MB fixed drives.|
|25/02/20||Major changes as I have implemented CPM and wrote the CBIOS / Ansi Terminal Emulator in the banked Rom. Currently beta level, CPM boots and runs fine, just the keyboard mappings need enhancing and some tweaks to the Ansi Terminal Emulator. Currently adding an SD Card into the hardware design and will add the software shortly thereafter.|
|23/8/19||Version 1.0 of the hardware and software are reliably running but Im in process of making a v1.1 PCB with corrections and additional logic to enable writing by the MZ80A to the Flash RAM.|
|SharpMZ||30/4/20||Placed one of the latest dev versions into gitlab/github and updated the Main_MiSTer code due to file handling changes made by collaborators.|
|7/6/19||Many fixes and updates have been made compared to the MiSTer_Devel released version 1.0 and started to add an IOCTL module so that the ZPU Evo can be embedded and take control of the emulator hardware. IOCTL is how MiSTer_Devel allows the HPS to control the target emulator so I’m keeping this mechanism in place for consistency.|
|tranZPUter||24/03/20||Debugged the hardware and made changes resulting in v1.1a of the hardware design. Slowly working out the FSM in VHDL to read/write between the FPGA and the Z80 Host. Also still waiting on me going Eureka and finding the bug in the L2 to L1 cache when using SDRAM!!!|
|15/12/19||Updated with the new ZPU Evo core and working SDRAM controller, 48K BRAM and 4MByte SDRAM so external applications can run (needed as main transZPUter app will run in SDRAM and more BRAM will be allocated to cache).|
|23/9/19||Waiting on the ZPU Evo. Hardware designed, tested and test ditties written to check that the FPGA can Master the Z80 Bus and utilize it’s hardware. Started the software (in C) framework based on the SharpMZ Emulator code.|
|ZPU Evo||28/01/20||The SDRAM, both vanilla and cached versions (1 row per bank cache) are working and pass all the memory tests at 100MHz. Unfortunately when using the SDRAM for program execution it highlighted a bug in the ZPU Evo which I have been trying to resolve. The bug is timing related and is between L2 to L1 and only shows up due to the timing delay of SDRAM. Using the cached SDRAM the bug is not so frequent but it needs resolving as the transzputer project needs SDRAM for applicaiton execution. To be resolved shortly!|
|23/12/19||Replaced megacore dual-port BRAM used for L2 cache with inferred RAM to aid in portability and updated write-thru to work at byte level (for self modifying code). Found and corrected a byte/half-word write bug which always defaulted to read-update-write. Changed the multiplication logic to meet timing (use of variable/combinational logic was causing significant negative slack impact). Fixed the timing for L2 Cache access. SDRAM now working for Wishbone and system bus reliably at 75MHz and meeting timing constraints. Still having issues running reliably > 75MHz no matter how the timing is arranged, still a work in progress. Used Signal Tap but cannot see reason. Still to add Burst mode for L2 Cache from SDRAM, design worked out using BRAM just have to code it.|
|31/10/19||The ZPU Evo is complete, I would say at Beta status until it is fully running in the SharpMZ project when I will stress it and add extra instructions. Debugging the WishBone SDRAM Controller, adding burst mode for L2 Cache Fill. Once the SDRAM Controller is fully working progress can be made on it’s dependents, for example the tranZPUter uses the Cyclone 10LP which has limited BRAM memory but an external 8M SDRAM chip so the SDRAM Controller is currently a showstopper.|
|dPWR||12/11/19||dPWR has been running reliably for 4 years, it needs tidying up a bit in terms of instructions, user guide and howto program additional modules/devices.|
|jDPWR||16/11/19||I started to write this Java version based on dPWR two years back but it got sidelined when I started the VHDL projects. I will finish it but no definite date yet.|
|MZ80A 80Col||23/8/19||Version 1.0 is reliable but I want to correct the control register access such that a write to the last bytes of attribute RAM doesnt occur when changing PCG bank or switching between 40/80 col.|
|ZPU Evo||tranZPUter||The tranZPUter uses the ZPU Evo as it’s primary soft processor|
|ZPU Evo||SharpMZ||The SharpMZ Emulator will have the ZPU Evo embedded to act as the IO and User Interface processor making the project less dependent on FPGA resources such as the embedded HPS on the Cyclone V.|
|CP/M||A000001||26/02/20||Ansi emulation not recognising clear screen.|
|ZPU Evo||C000001||28/01/20||L2 to L1 timing results in one 32bit word being incorrectly placed in the L1 cache. The bug occurs on program jumps and the word is from the previous next of PC location. Only occurs when using SDRAM.|
|MZ80A 80Col||H000001||23/08/19||A write to the control register bleeds into the attribute ram as they share the same location. Needs a coded latch to seperate the write signals.|